Video makes up 50% of the time spent on Meta Family of Apps, with more than 4B video views per day. Improving the compression efficiency of video encoding while still delivering high quality videos at “billion scale” is critical to reducing the cost of data-usage for both end-users and infrastructure providers, as well as doing so in an environment-friendly manner. This is where hardware acceleration thrives as application-specific integrated circuits (ASICs), which offer very high energy efficiency for at scale deployment at Meta. In this workshop, we will introduce the Meta Scalable Video Processor (MSVP), the first generation server grade video processing hardware accelerator developed at Meta. We will review its algorithm and architecture, and will show how it plays a role in achieving high-quality video encoding at Meta’s video production pipeline.
Agenda
- Opening Remarks: Video at Meta
- Encoder Algorithm Tuning
- MSVP: Meta Scalable Video Processor
- Q&A
Speakers’ short biographies
Visala Vaduganathan is an ASIC Engineer in Meta’s Infra Silicon Design Team contributing to architecture and design for Video Transcoder and Quality Metrics silicon solutions. Visala has worked on several scalable video codec silicon catering to high performance, low power, low area requirements. Prior to joining Meta, Visala worked on video codecs for mobile processors in Qualcomm and early chips of the family of Tegra processors in Nvidia. Visala has a Master’s Degree in Electrical Engineering from San Jose State University and a Bachelor’s Degree in Electronics and Instrumentation from Annamalai University, India.
Rohan Mallya is an ASIC Design Engineer at Meta's Infra Silicon team where he has been working on architecting and designing custom silicon for Video Transcoding in Meta's data centers for the last 4 years. Prior to joining Meta, Rohan spent 9 years at Qualcomm designing Multimedia IP part of the company's Snapdragon line of mobile processors. Apart from his silicon design expertise, Rohan is well versed with Video Codecs with an emphasis on hardware friendly Video encoders. He received his Master's in Computer Engineering from North Carolina State University in 2009 specializing in ASIC Design.
Guogang Hua is an engineer at Meta infra Silicon team. He’s spent the last four years in Meta to build Meta’s first video accelerator; He’s also been working on supporting firmware/software and production of the video accelerator. Prior to joining Meta, he spent 10 years at Qualcomm to build video encoder/decoder inside Snapdragon SOCs, which are being used in billions of devices. He received his B.S. and M.S. from the University of Science and Technology of China, and Ph.D. from Florida Institute of Technology.
Hsiao-Chiang Peter Chuang is an engineer at Meta’s Infra Silicon Team focusing on modeling and algorithm development of video codecs. Prior to joining Meta, he spent five years working on encoder algorithm design for Qualcomm Snapdragon SOCs, and spent another three years on the development of coding tools for next-generation video codecs at both Qualcomm and Bytedance. He received his Ph.D. in Electrical and Computer Engineering from Purdue University in 2011.